In a computer system including a CPU and a memory subsystem, a network controller communicates with the CPU and the memory via a PCI bus. In particular, the CPU writes and reads various control and status bits to and from multiple registers in the network controller to initiate and complete frame transmission and reception, to ascertain the status of the network controller, and to control its functions.
Direct access to registers in the network controller via a PCI bus substantially slows the operation of the CPU. Therefore, it would be desirable to arrange the registers so as to reduce the impact of such access on the CPU performance.